Multi-layer inductor formed in a semiconductor substrate and having a core of ferromagnetic material

ABSTRACT

A thin-film multilayer high-Q inductor having a ferromagnetic core and spanning at least three metal layers is formed by forming a plurality of parallel first metal runners on the semiconductor substrate. A plurality of first and second vertical conductive vias are formed in electrical connection with each end of the plurality of metal runners. A plurality of third and fourth conductive vias are formed over the plurality of first and second conductive vias and a plurality of second metal runners are formed interconnecting the plurality of third and fourth conductive vias. The first metal runners and second metal runners are oriented such that one end of a first metal runner is connected to an overlying end of a second metal runner by way of the first and third vertical conductive vias. The other end of the second metal runner is connected to the next metal one runner by way of the second and fourth vertical conductive vias., forming a continuously conductive structure having a generally helical shape. An inductor core is formed by first forming a silicon layer between each one of the plurality of first metal runners. A germanium layer is formed thereover and the structure is annealed, causing formation of quantum dots of germanium. A cobalt layer is then formed over the quantum dots and another anneal process drives the cobalt into the quantum dots, where it is captured to form the ferromagnetic core.

This patent application claims priority to the provisional patentapplication filed on May 7, 2002, and assigned Ser. No. 60/378,476.

FIELD OF THE INVENTION

This invention relates generally to inductors, and more specifically, toinductors having a core of ferromagnetic nano-crystals.

BACKGROUND OF THE INVENTION

The current revolution in wireless communications and the need forsmaller wireless communications devices have spawned significant effortsdirected to the optimization and miniaturization of radio communicationselectronic devices. Passive components (such as inductors, capacitorsand transformers), play a necessary role in the device's operation andthus efforts are directed toward reducing the size and improving theperformance and fabrication processes for such components.

Discrete inductors, which play an integral role in the performance ofthese communications devices, are electromagnetic components comprisinga plurality of windings typically enclosing a core constructed of eithermagnetic material or an insulator. The inductance of an inductor is ameasure of the inductor's opposition to changes in the existing current.Use of a magnetic core yields higher inductance values than corescomprised of an insulator, such as air. Typical cores are formed offerromagnetic material (e.g., iron, cobalt, nickel). These materialscomprise a plurality of magnetic domains, and the application of amagnetic field to the core material causes domain alignment and aresulting increase in the material permeability, which in turn increasesthe inductance. The inductance is also a function of the number of coilturns (specifically, the inductance is proportional to the square of thenumber of turns), the core size and the core material. Conventionalinductors are formed as a helix (also referred to as a solenoidal shape)or a torroid.

With the continual allocation of operational communications frequenciesinto higher frequency bands, inductor losses increase due to increasededdy current and skin effect losses. To avoid these losses at relativelylow operational frequencies, the inductive effect can be simulated byemploying certain active devices. But simulated inductors are moredifficult to realize at higher frequencies, have a finite dynamic rangeand inject additional unwanted noise into the operating circuits.

The Q (or quality factor) is an important inductor figure of merit. TheQ is a function of the ratio of inductive reactance to inductiveresistance, and indicates the sharpness of the inductor's resonance.High Q inductors present a narrow resonant peak when the inductorcurrent is graphed as a function of the input signal frequency, with thepeak representing the inductor resonant frequency. High Q inductors areespecially important for use in frequency-dependent circuits operatingwithin narrow signal bandwidths. Because the Q value is an inversefunction of inductor resistance, it is especially important to minimizethe resistance to increase the Q.

Most personal communications devices incorporate integrated circuitsfabricated using semiconductor technologies, such as silicon orgallium-arsenide. In the past, integrated planar inductors (includingtorroidal or spiral shapes) have been employed to achieve compatibilitywith the silicon-based integrated circuit fabrication processes.However, these planar inductors tend to suffer from high losses and lowQ factors at the operational frequencies of the communications devices.These losses and low Q factors are generally attributable to dielectriclosses caused by parasitic capacitances and resistive losses due to theuse of thin and relatively high resistivity conductors. Also, themagnetic field lines generated during operation of a planar inductor areperpendicular to the major surface of the semiconductor substrate, alongwhich the active devices are formed. These are closed-loop magneticfield lines that enter the material above, laterally adjacent and belowthe inductor. Field penetration through dielectric materials of theintegrated circuit increases the inductive losses thereby lowering theinductor's Q factor. Also, if the inductor is not sufficiently spacedapart from active circuit elements of the integrated circuit, themagnetic fields can induce currents in and affect operation of theactive elements.

As integrated circuit active devices grow smaller and operate at higherspeeds, the interconnect system can disadvantageously add processingdelays to the device signals. In this regard, as the circuit functionsdemand a greater number of interconnects and as the interconnectcross-section shrinks, conventional interconnect metallizationmaterials, e.g., aluminum, severely limit circuit speeds. Further, therelatively small contact resistance between the aluminum and silicon canbe a significant contributor to the total circuit resistance, especiallyas the number of circuit components and interconnects increases.Finally, as line widths continue to shrink, it becomes increasinglydifficult to deposit aluminum within high aspect ratio vias and plugs.

Given theses disadvantages, copper is becoming the material of choicefor metallization. It is a better conductor than aluminum (with aresistance of 1.7 micro-ohm cm compared to 3.1 micro-ohm cm foraluminum), is less susceptible to electromigration, can be deposited atlower temperatures (thereby avoiding deleterious effects on the devicedopant profiles) and is suitable for use in high aspect ratioapplications. Copper interconnects can be formed by chemical vapordeposition, sputtering, electroplating and electrolytic plating.

The damascene process is one technique for forming copper interconnectsfor integrated circuits. A trench is formed in a surface dielectriclayer and copper material is then deposited in the trench. Usually thetrench is overfilled, requiring a subsequent chemical/mechanicalpolishing step to replanarize the dielectric surface. This process ofdepositing copper in a trench offers superior dimensional controlbecause it reduces dimensional variations relative to variations thatare introduced in a typical subtractive metal etch process.

Dual damascene copper processes integrally form both the verticalconductive via portion and the substantially horizontal metalinterconnect portion of an interconnect system. The via opening isformed first, followed by formation of an overlying trench. A subsequentmetal deposition step fills both the via opening and the trench, forminga complete metal layer. A chemical/mechanical polishing step planarizesthe deposited metal with respect to the adjacent dielectric surface.

BRIEF SUMMARY OF THE INVENTION

A method for forming an integrated circuit structure comprises providinga semiconductor substrate having an upper surface. A first plurality ofconductive lines are formed in a first layer overlying the uppersurface. A second plurality of conductive lines are formed in a secondlayer spaced apart from and overlying the first layer. The first and thesecond plurality of conductive lines are interconnected to form ahelical conductor structure. A core material layer exhibitingferromagnetic properties is formed between the first and the secondlayers.

An integrated circuit structure formed according to one embodiment ofthe present invention comprises a semiconductor substrate and a helicalconductor formed over the substrate. A core exhibiting ferromagneticeffects is formed in a region bounded by the helical conductor.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more easily understood and the advantagesand uses thereof more readily apparent, when considered in view of thefollowing detailed description when read in conjunction with thefollowing figures wherein:

FIGS. 1 through 41 illustrate, in a cross-sectional view taken along acommon plane or in a plan view when so noted, an inductor structureaccording to one fabrication embodiment of the present invention duringsequential fabrication steps.

FIGS. 42 through 44 illustrate top views of alternative inductorstructures formed according to the teachings of the present invention.

FIGS. 45 through 48 illustrate sequential fabrication steps of aninductor structure according to another fabrication embodiment of thepresent invention.

FIGS. 49 through 53 illustrate sequential fabrication steps of aninductor structure according to yet another fabrication embodiment ofthe present invention.

In accordance with common practice, the various described devicefeatures are not drawn to scale, but are drawn to emphasize specificfeatures relevant to the invention. Reference characters denote likeelements throughout the figures and text.

DETAILED DESCRIPTION OF THE INVENTION

One process for forming an inductor according to the present inventionbegins as shown in FIG. 1, where a plurality of layers are formed overan existing integrated circuit semiconductor substrate 19 thatconventionally includes a plurality of active regions (not shown). Inone embodiment according to the teachings of the present invention,fabrication of the inductor begins after formation of the various dopedregions, but prior to the formation of metal interconnect layers forconnecting the doped regions to form active devices. This sequence offabrication process steps is not required for implementation of thepresent invention, but rather is set forth as one example.

A barrier layer 20 overlies an upper surface of the semiconductorsubstrate 19 and is preferably formed from one or more layers oftantalum, tantalum-nitride, titanium or titanium-nitride. Next aninsulating layer 22, preferably formed from a material having arelatively low dielectric constant, is formed over the barrier layer 20.Certain forms of silicon dioxide exhibiting a low dielectric constantcan be used for the insulating layer 22. The relative dielectricconstant for silicon dioxide is normally about 3.9. A low relativedielectric constant is generally considered to be less than about 3.0.Use of a low dielectric constant material reduces inter-layercapacitance and therefore potential cross-talk between signals carriedin conductive structures proximate the insulating layer 22. However, inanother embodiment, conventional silicon dioxide can be used. Thebarrier layer 20 and the insulating layer 22 can be formed by chemicalvapor deposition or other known processes.

A hard mask layer 24, conventionally comprising silicon dioxide,overlies the insulating layer 22. To etch a layer or layers below a hardmask photoresist material is applied over the hard mask the photoresistis patterned and the pattern is transferred from the photoresist to thehard mask. The photoresist is removed and etching steps are performedusing the hard mask pattern. This process advantageously offers betterdimensional control of the etched features than the conventional mask,pattern and etch processes, which can, however, be used in lieu of thehard mask. Using either process, a plurality of parallel windows ortrenches 25 are formed by etching the insulating layer 22 and the hardmask layer 24. An exposed region of the barrier layer 20 at the bottomof the trenches 25 is removed in a subsequent etch step. One such trenchis shown in the cross-sectional view of FIG. 2. A plurality of trenches25 are illustrated in the top view of FIG. 3. Preferably, in the topview the plurality of trenches 25 are square or rectangular as shown inFIG. 3, but circular or elliptical shapes may be formed ifphotolithographic limitations, e.g., diffraction effects, do not allowformation of sharp cornered structural shapes. Thus although illustratedas rectangular or square in subsequent figures, windows and trenches,when viewed from the top, can be circular, elliptical, or presentrelatively straight edges and rounded corners.

Although the following description refers only to the trench 25 shown inthe FIG. 2 cross-section, it should be apparent that each of theplurality of parallel trenches 25 shown in FIG. 3 simultaneouslyundergoes the same processing steps. As shown in FIG. 4, a siliconbuffer layer 26 is formed in the trench 25 of FIG. 2, for example, byepitaxially growing the silicon from the underlying silicon substrate19. It is not necessary for the silicon seed layer (i.e., the siliconsubstrate 19) to exhibit a specific crystal orientation, although aMiller Index of <111> is preferred. As discussed below, while the use ofother crystalline orientations does not require a change in the processsteps to form the quantum dots, the crystal orientation does affect thesize and spacing of the formed dots. As shown in FIG. 4, the siliconbuffer 26 extends laterally beyond the side walls of the trench 25.

Lacking a silicon seed layer, silicon does not grow in regions 25A (seeFIG. 3) between the parallel trenches 25, and regions 25B laterallyadjacent the trenches 25, as the hard mask 24 forms the upper layer inthe regions 25A and 25B.

The regions 25A and 25B and all other regions of the substrate surface,exclusive of the silicon buffers 26 (which are the growth surfacesduring subsequent process steps) are masked with a photoresist 27 toprevent processing in these regions. See FIG. 5 where the photoresist 27is shown in the regions 25B laterally adjacent side walls 28 of thesilicon buffer 26.

As shown in FIG. 6, a thin germanium wetting layer 29 is deposited overa top surface of the silicon buffer 26 and the photoresist 27.Preferably this layer is about 5 to 30 Angstroms thick, i.e., a fewmonoatomic layers. The germanium layer 29 may be formed by aconventional plasma vapor deposition process or another know technique.

During the next several processing steps the germanium layer 29 ispatterned. In FIG. 7, a hard mask layer 30 is deposited over the uppersurface of the structure. A photoresist layer 31 is deposited, exposed,patterned and etched, resulting in the structure illustrated in FIG. 8.

As illustrated in FIG. 9, the hard mask layer 30 is etched to verticallyalign the side walls 30A thereof with the side walls 28. The photoresistlayer 31 is removed and the resulting structure illustrated in FIG. 10.

As shown in FIG. 11, the germanium layer 29 is etched back so that sidewalls 29A thereof are aligned with the side walls 28 and 30A. The hardmask layer 30 is removed, and the resulting structure illustrated inFIG. 12.

The structure is then annealed, preferably at a temperature betweenabout 400 and 500° C. for about 5 to 10 minutes. The material of thephotoresist layer 27 is selected to match the conditions of the annealprocess such that the photoresist 27 is not detrimentally affected bythe anneal. The anneal process forms a matrix of germanium quantum dots32 (also referred to as semiconductor material islands). The quantumdots 32 are elemental germanium islands formed by the preferentialgrowth of the germanium at steps and out-of-phase boundaries on the topsurface of the silicon buffer 26 during the surface bond reconstructionprocess that occurs during the anneal. See FIG. 13.

About a few monolayers of ferromagnetic material 33 are deposited (forinstance by plasma vapor deposition) at room temperature over thequantum dots 32, as shown in FIG. 14. Preferably the ferromagneticmaterial 33 is about 1–5 atomic layers thick Nickel, iron, cobalt andgadolinium are all suitable ferromagnetic materials. Other elements andcompounds that exhibit ferromagnetic properties are also suitable, butfor purposes of illustration, the process is described using cobalt asthe ferromagnetic material 33.

The process continues with the deposition of a dielectric layer 35 asshown in FIG. 15. A photoresist layer is deposited over the dielectriclayer 35 and exposed, patterned, and etched to form the photoresistlayer 36 illustrated in FIG. 16. According to the next process step, thedielectric layer 35 is etched back to vertically align the side walls35A thereof with the side walls 28. See FIG. 17. The photoresist layer36 is then removed. The structure at this point in the process is shownin FIG. 18.

Exposed regions 33A of the ferromagnetic material 33 are removed byetching. The dielectric layer 35 is then removed, also by etching. Thestructure at this point in the process is illustrated in FIG. 19,illustrating the quantum dots 32 and the ferromagnetic material 33.

The structure is annealed at about 400–500° C., for five to ten minutes,during which a cobalt-germanium phase layer forms within the quantumdots 32. Different combinations of anneal temperature and annealduration can be used to form the metal-germanium phase layer. Due to thelow anneal temperature, the germanium does not react with the underlyingsilicon buffer 26 to form a SiGe alloy. The anneal process causes thecobalt to diffuse downwardly to the silicon-germanium interface, where athin CoSi2 (cobalt-silicide) layer is formed within the quantum dots 32.See FIG. 20 where the captured cobalt is identified by a referencecharacter 34. Selective sputtering removes any silicide between adjacentquantum dots 32. The resulting structure comprises a layer of germaniumquantum dots 32 with CoSi2 34 completely encapsulated therein.

Each Ge/CoSi2 quantum dot 32/34 is a flat-band energy structure in whichthe electrons are confined three-dimensionally inside a region that issurrounded by high potential energy regions. Thus the Ge/CoSi2 quantumdots 32/34 containing a single, three-dimensionally confined electroncan be considered an individual magnetic domain. Different combinationsof anneal temperature and duration can be used to form the Ge/CoSi2quantum dots 32/34, but the anneal step must be compatible with theback-end fabrication steps where it is know that the use of hightemperatures can disturb the active region dopant profiles and impairpreviously-formed metal interconnect layers. Also, the annealtemperature and duration can affect the size and spacing of the Ge/CoSi2quantum dots. This process of forming quantum dots through an annealstep is known in the art. See for example, 1. H. Hibino and T. Ogino,Appl. Phys. Lett., vol. 67 no. 7, 1995, pp. 915–917; U. Kohler, J. E.Demuth, and R. J. Hamers, J. Vac. Sci. Technol. A, vol. 7 no. 4, 1989,pp. 2860–2867; J.-H. Zhu, K. Brunner, and G. Abstreiter, Mat. Res. Soc.Symp. Proc., vol. 533, 1998, pp. 165–170.

To form quantum dots according to other embodiments of the presentinvention other semiconductor materials and compound semiconductormaterials can be used in lieu of the germanium, including any of thegroup III–V compound semiconductors such as GaAs, InAs, GaInAs, AlAs,and GaAlAs, the group IV semiconductors such as Si and SiGe and thegroup II–VI compound semiconductors such as CdTe.

The resulting captured cobalt-silicide (or in another embodiment thesilicide of another ferromagnetic material) is in a stable single domainconfiguration and thus exhibits ferromagnetic properties. Due to thepresence of the captured cobalt-silicide in the inductor core, theinductor coercive fields are approximately eight times the value absentthe ferromagnetic core. Although the cobalt-silicide islands are singlemagnetic domains, coupling between individual Ge/CoSi2 quantum dots32/34 produces characteristics similar to a continuous ferromagneticmaterial, resulting in a further increase in the ferromagnetic effectexhibited by individual Ge/CoSi2 quantum dots 32/34.

In addition to the processes set forth above for forming the Ge/CoSi2quantum dots 32/34, similar, and possibly more advantageousconfigurations may be produced, such as by: deposition of a magneticfilm on a flat wafer and etching to form quantum dots (O. Kazakova, M.Hanson, P. Bloomquist, and R Wappling, J. Appl. Phys. 90, p. 2440–2446,2001), deposition of a magnetic film on an array of silicon dotsprepared by electron beam lithography and reactive etching (S. Landis,B. Rodmacq, and B. Dieny, Phys. Rev. B 62, p. 12271–12281), andelectrodeposition of ferromagnetic material on silicon electrodes (C. A.Moina and M Vazdar, Electrochemistry Comm. 3, p. 159–163, 2001).

In another embodiment it may be unnecessary to enclose ferromagneticmaterial within the Ge/CoSi2 quantum dots 32/34 to form an inductor coreexhibiting ferromagnetic effects. For example, it is known that arraysof semiconductor material in the form of islands on a semiconductorsurface also exhibit ferromagnetic properties. See H. Tamura, K.Shiraishi and H. Takayanagi, Jap. J. Appl. Phys, Part 2-Letters, vol. 39no. 3AB, 2000, pp. L241–243. Thus according to such an embodiment of thepresent invention, the quantum dots 32 form an inductor core without theuse of the ferromagnetic material captured therein.

As shown in FIG. 21, a silicon layer 37 is deposited or grown over theGe/CoSi2 quantum dots 32/34. Note that the side walls 37A of the siliconlayer 37 are shown in FIG. 21 as vertically aligned with the side walls28. In an embodiment where the silicon layer 37 is grown from thesilicon buffer 26, the structure of FIG. 21 results. In anotherembodiment using a silicon deposition process, the silicon layer 37extends laterally beyond the side walls 28 to the edges of the FIG. 21structure. In this latter embodiment, it would be advantageous toexecute a series of known masking, patterning, and etching steps toremove regions of the silicon layer 37 such that in the resultingstructure the side walls 37A are vertically aligned with the side walls28.

In an embodiment where an inductor core segment 40A comprises a singlelayer of the Ge/CoSi2 quantum dots 32/34, fabrication of the inductorcore segment 40A is complete. In the top view of FIG. 22 a core 40comprises a plurality of the parallel core segments 40A–40F. Thecross-sectional view of FIG. 21 is taken along a plane 21/21 of FIG. 22.

The photoresist mask 27 is removed for subsequent processing steps toform substantially horizontal conductive runners and substantiallyvertical conductive vias, together which form the inductor windingsenclosing the inductor core 40. The resulting structure after removal ofthe photoresist mask 27 is illustrated in FIG. 23. In anotherembodiment, it may be necessary to remove the hard mask layer 24 to formthe conductive runners and vias. The formation of the conductive runnersand vias is explained below in conjunction with another embodiment ofthe invention.

In an embodiment where the core 40 comprises additional layers ofGe/CoSi2 quantum dots 32/34, the photoresist mask 27 is retained and theprocess steps set forth above are repeated to sequentially formadditional vertically disposed layers of the Ge/CoSi2 quantum dots32/34. In this embodiment, the height of the photoresist mask 27 isincreased to accommodate the higher quantum dot stack.

The next layer of the Ge/CoSi2 quantum dots 32/34 is formed over thesilicon layer 37, which serves as a substrate for the overlying layer ofGe/CoSi2 quantum dots 32/34. The process steps are substantiallyidentical to those described above for formation of the first layer ofGe/CoSi2 quantum dots 32/34. A germanium layer is deposited on thesilicon layer 37, patterned and etched, then annealed to form thequantum dots 32. A layer of ferromagnetic metal (cobalt, for example) isdeposited and annealed to form the Ge/CoSi2 quantum dots 32/34. Anoverlying silicon layer is grown or deposited to serve as a substratefor the next vertical layer of quantum dots.

Four such layers of quantum dots 32/34 forming an inductor core segment40A are shown in FIG. 24. The addition of more layers of Ge/CoSi2quantum dots 32/34 or an increase in the concentration of the germaniumin each germanium layer 33 (e.g., by increasing the size of ordecreasing the distance between the quantum dots 32) increases thepermeability of the inductor core segment 40A, and thus the permeabilityof the core 40 and the inductance.

In preparation for forming the conductive runners and vias that form theinductor windings, the photoresist mask 27 is removed, as shown in FIG.25. It may also be necessary to remove the hard mask layer 24.

A region 41 (see FIG. 25) of the multilayer inductor core segment 40A(and the other segments 40B–40F parallel thereto) extending beyond dieside walls of the trench 25 can be removed by employing conventionalmasking, patterning and etching steps. The result is a core segment 40Athat is aligned with the trench side walls 28A as shown in FIG. 26. Inthe top view the structure is illustrated in FIG. 27, where theplurality of multilayer core segments 40A–40F comprise the mukilayerinductor core 40. FIG. 26 is taken along a plane 26/26 of Figure 27.

In the subsequent process steps the conductive runners (also referred toas conductive leads, lines, or strips) and vias are formed. In apreferred embodiment employing the damascene (or dual damascene)process, the lower and upper conductive runners are interconnected bythe conductive vias to form the inductor windings. The core segments40A–40F are disposed within an open region defined by the conductiveelements of each winding.

A trench 42 (for carrying a lower conductive runner) is formed in theinsulating layer 22 surrounding each inductor core segment 40A–40F. Seethe cross-sectional view of FIG. 28 and the FIG. 29 plan view, where theFIG. 28 cross-section is taken along the plane 28/28 of FIG. 29. FIG. 29illustrates a plurality of trenches 42 formed surrounding each one ofthe plurality of parallel inductor core segments 40A–40F. As can also beseen in FIG. 29, an insulating layer 44 is formed between each of thetrenches 42. Although the inductor core segments 40A–40F and thetrenches 42 in FIG. 29 are shown parallel with a front surface 45 of thesubstrate, this orientation is not necessarily required.

In another embodiment a trench for a lower runner is formed between eachof the plurality of parallel core segments 40A–40F. See FIG. 30. Therelative size and spacing of the trenches 42 and the core segments40A–40F can be varied. With reference to FIG. 30, conductive vias arelater formed generally in regions 46. Upper conductive runners areformed in electrical communication with the conductive vias such thatone upper conductive runner interconnects two consecutive lowerconductive runners through the vias.

Subsequent steps for fabricating the inductor windings involve only theconductive structures, therefore the inductor core segments 40A–40F aremasked, as required, to avoid deleterious effects from subsequentprocess steps.

As shown in FIG. 31, a barrier layer 50 and a seed layer 51 aredeposited along the side walls and bottom of the trenches 42. Thematerial of the barrier layer 50 is sputtered into the trench 42.Tantalum, tantalum-nitride, titanium and titanium-nitride are candidatematerials for the barrier layer 50. Next, a thin copper seed layer 51 isdeposited, preferably by sputtering. The seed layer 51 is advantageousas a starting layer for the subsequent electroplating of copper.Alternatively, the barrier layer 50 and the seed layer 51 may bedeposited by conventional chemical vapor deposition or electroplatingprocesses.

A metal-1 conductive runner 52 is formed in the trench 42, preferably byelectroplating copper. The substrate is then chemically-mechanicallypolished to remove the electroplated copper from all regions exceptwithin the trench 42. Because the chemical/mechanical polishing (CMP)step is selective to the copper material, the ferromagnetic core 40 thatlies behind and extends above the metal-1 runner 52 is not affected bythe CMP process.

In another embodiment, not shown, the conductive runner is formed priorto forming the inductor core of Ge/CoSi2 quantum dots 32/34.

Additional details regarding damascene processing are discussed in C. K.Hu et. al., Proceedings MRS Symposium on VLSI, vol. 5, p. 369 (1990); B.Luther et. al., Proceedings VMIC, vol. 10, p. 15 (1994); D. Edelstein,Proceedings ECS Mtg., vol. 96–2, p. 335 (1996), all of which areincorporated by reference. It is not necessary, however, to employ adamascene process to form the various metal layers of the inductor. Inanother embodiment, conventional subtractive metal etch processing stepsmay be employed.

In certain circuit configurations it may be necessary to connect themetal-1 runner 52 to underlying active device regions in the substrate.For example, one end of the metal-1 runner may serve as an inductorterminal for connection to another circuit component. This can beeffected in a dual damascene process by first forming a via opening toan underlying device region. Subsequently a trench, e.g., the trench 42,is formed and the via opening and the trench portion are simultaneouslyfilled with conductor, e.g., electroplated copper, to form an underlyingconductive via connected to the metal-1 runner 52. Thus electricalconnections to the metal-1 runner 52 serve as terminals for theinductor.

As shown in FIG. 32, a five-layer stack comprising deposited layers 53,54, 55, 56 and 57 is formed over the entire region of the substratewhere the inductor is to be formed, including the region overlying themetal-1 runner 52, the adjacent exposed regions of the hard mask layer24 and the inductor core 40. The five-layer stack has a generallyconformal shape over the inductor core 40.

To form this stack, a barrier layer 53 (preferably of titanium-nitride)is deposited and an insulating layer 54, preferably having a relativelylow dielectric constant, is formed over the barrier layer 53. An etchstop layer 55, for example silicon-nitride, is formed over theinsulating layer 54. Another low-dielectric constant insulating layer56, is formed over the etch stop layer 55. A hard mask layer 57 isformed over the insulating layer 56. As discussed above, conventionalphotoresist and masking material can be used in lieu of the hard-masklayer 52.

The hard mask layer 57 is patterned to define areas where openings 60and 62 are to be formed. See FIG. 33. The openings 60 and 62 extenddownwardly to the barrier layer 53, and the exposed regions of thebarrier layer 53 are removed by etching. Typically, at this point in theintegrated circuit fabrication process there are other areas of theintegrated circuit that require metal-2 layer interconnects withunderlying device regions, and thus the via openings for thoseinterconnects are patterned and etched when the via openings 60 and 62are formed.

As illustrated in FIG. 34, a barrier layer 64 and a seed layer 65 aredeposited within the via openings 60 and 62. The process and materialsare identical to those discussed in conjunction with the barrier layer50 and the seed layer 51 of FIG. 31. Copper is then preferablyelectroplated within the via openings 60 and 62, followed by a chemicaland mechanical polishing step to planarize the top surface. The copperregions in the lower portion of the openings 60 and 62 are referenced inthe Figures as conductive vias 66 and 67. The copper regions in theupper portion of the openings 60 and 62 is referenced in the Figures asmetal-2 vias 68 and 69.

If required, a CMP step is performed to planarize a top surface 70 ofthe substrate before formation of the subsequent layers. FIG. 35illustrates the substrate after the CMP step.

As shown in FIG. 36, a multilayer stack comprising layers 71, 72, 74, 76and 78 is formed over the existing layers, where the material of theindividual layers is preferably identical to the materials used in themultilayer stack discussed in conjunction with FIG. 17. In particular,the layers formed sequentially include a barrier layer 71, an insulatinglayer 72 (preferably comprising material having a low dielectricconstant), an etch stop layer 74, an insulating layer 76 (againpreferably comprising a low dielectric constant material, and a hardmask layer 78. Conventional photoresist and masking processes can beused in lieu of the hard mask layer 78 to pattern and etch the surface.

As illustrated in FIG. 37, via openings 84 and 86 are formed within themultilayer stack, using the hard mask layer 78 to pattern and etch thesurface such that the via opening 84 is aligned with the top surface 88of the metal-2 conductive via 68, and the via opening 86 is aligned withthe top surface 89 of the metal-2 conductive via 69. The exposed regionsof the barrier layer 71 within the via openings 84 and 86 is removed.

A trench 100 extending downwardly to the etch stop layer 74 is formed inthe stack of layers as illustrated in FIG. 38. It is known that toeffectively stop the etch process at the etch stop layer 74 the etchbyproducts are analyzed. When the material of the etch stop layer 74 isdetected the etch process is terminated.

The orientation of the trench 100 with respect to successive metal-1runners 52 and metal-2 conductive vias 68 and 69 is shown in the topview of FIG. 39, with FIG. 38 illustrating a cross-section view alongthe line 38/38 of FIG. 39. Thus it will be seen that the conductivematerial formed later in the trench 100, as described below,interconnects two successive metal-1 runners 52 through the conductivevias 68/66 (left side) and 69/67 (right side). The orientation of thecore 40 relative to the metal-1 runners 52 is illustrated in twoembodiments: the embodiment of FIG. 29 wherein the metal-1 runners 52(formed in the trench 42) surround core segments 40A-40F; the embodimentof FIG. 30 wherein a metal-1 runner is disposed between each coresegment 40A-40F.

As shown in FIG. 40, a barrier layer 103 is deposited to limit thediffusion of the copper (later formed in the trench 100) into thesurrounding insulating layers. The material of the barrier layer 103(tantalum, tantalum-nitride, titanium and titanium-nitride are candidatematerials) is sputtered along the side walls and bottom of the viaopenings 84 and 86. Next a thin copper seed layer 104 is deposited,preferably by sputtering, to serve as a starting layer for thesubsequent copper electroplating. Alternatively, the barrier layer 103and the seed layer 104 may be deposited by conventional chemical vapordeposition or electroplating processes. It is not necessary to form abarrier layer along the bottom surface of the trench 100, as the etchstop layer 74 serves the barrier purpose. Also the plating seed layer isnot required on the bottom surface of the trench 100 because copper willelectroplate laterally from the side walls of the via openings 84 and86.

Copper is deposited, preferably by electroplating, filling the viaopenings 84 and 86 to form conductive vias 106 and 107, metal-3 vias 108and 109 and a metal-3 runner 110 therebetween. See FIG. 41. Thestructure is then chemically-mechanically polished to remove copper fromthe unwanted field areas of the substrate and planarize a top surface112.

The metal-3 runner 110 interconnects two consecutive parallel metal-1runners 52, as shown in the top view of FIG. 42, resulting in a helicalconductor structure. In this embodiment, the inductor core segments40A-40F are disposed between successive metal-1 runners 52 and below themetal-3 runner 110. Only one core segment 40A is illustrated in FIG. 42.In the embodiment illustrated, the metal-1 runner 52 is substantiallyrectangular with diagonal interconnecting metal-3 runners 110,resembling the letter “Z” in the top view. The metal-3 runner 110interconnects successive metal-1 runners 52 via a vertical conductivestack 120 (comprising the conductive via 67, the metal-2 via layer 69,the conductive via 107 and the metal-3 via layer 109) and the verticalconductive stack 122 (comprising the conductive via 66, the metal-2 vialayer 68, the conductive via 106 and the metal-3 via layer 108), to forman inductor winding 123. Additional windings similar to and electricallyconnected to the winding 123 are juxtaposed to form an inductor having acore comprising Ge/CoSi2 quantum dots.

In yet another embodiment, illustrated in FIG. 43, the metal-1 andmetal-3 runners 52 and 110 are interconnected in a zig-zag pattern toform an inductor winding 130.

In the embodiment illustrated in the top view of FIG. 44, the metal-1runners 52 and the metal-3 runners 110 are both substantially L-shapedand interconnected at a first end by the vertical conductive stack 120,comprising the conductive via 67, the metal-2 via layer 69, theconductive via 107 and the metal-3 via layer 109. At a second end themetal-3 runner 110 is electrically connected to the next successivemetal-1 runner 52 via the vertical conductive stack 122, comprising theconductive via 66, the metal-2 via layer 68, the conductive via 106 andthe metal-3 via layer 108. The inductor core segment 40A is disposedbetween the metal-1 runners 52 and below the metal-3 runner 110. Aplurality of the FIG. 44 windings are juxtaposed and electricallyconnected to form an inductor comprising a plurality of windings andcore segments.

Although the Figures and accompanying description herein illustrateplacement of the bottom and top metal layers of the inductor in themetal-1 and metal-3 layers of the integrated circuit, the inventivefeatures of the present invention can be applied such that the inductorspans other metal layers, for example, the bottom segment of an inductorwinding can be placed within the metal-2 layer and the top segment ofthe winding can be placed within the metal-4 layer or the metal-5 layer.Other embodiments where different metal layers and a different number ofmetal layers are spanned are considered within the scope of the presentinvention.

Although formation of the inductor according to the present inventionhas been described using a damascene process, the invention is notlimited thereto. The inductor windings can also be formed usingconventional metal deposition and subtractive etch steps wherein themetal layers forming the top and bottom winding segments areinterconnected by vertical vias spanning the metal layers. Furtherdetails of the process for forming the inductor windings can be found inthe commonly-assigned patent application entitled A Multi-Layer InductorFormed in a Semiconductor Substrate, filed on Oct. 5, 2001, and bearingapplication Ser. No. 09/972,482.

Another process for forming a ferromagnetic core begins with thestructure illustrated in FIG. 45, which is identical to the structure ofFIG. 5, including the silicon buffer 26. All areas, except the growthsurface of the silicon buffer 26, are masked with photoresist 27 toprevent processing in the masked regions. As shown in FIG. 46, an SiO₂layer 150 about 1 nm thick is deposited or grown over the silicon bufferlayer 26. Next a layer 152 comprising 1–5 monolayers of cobalt (oranother ferromagnetic material) is deposited over the SiO₂ layer 150.

The structure is annealed at about 375–425° C., to diffuse the cobaltthrough the SiO₂ layer 150 and into the silicon buffer 26, where itreacts with the silicon to form a layer of CoSi2 153, primarily at theSiO2/silicon interface. See FIG. 47. This process of cobalt reactingwith silicon to form cobalt-silicide is known in the art. (See R Hibinoand T. Ogino, Appl. Phys. Lett. Vol. 67 no. 7 1995, pp. 915–917). Afterformation of the CoSi2 layer 153, the SiO2 layer 150 can be removed.

If a multilayer inductor core is to be formed, the process continues byrepeatedly forming an epitaxial layer of silicon on the surface of thesilicon dioxide layer 150, followed by formation of a cobalt layer. Thestructure is annealed to form another layer of cobalt-silicide in theepitaxial silicon layer. An inductor core 154 formed according to thisprocess and comprising a plurality of cobalt-silicide layers 153, 153A,153B, 153C, 153D and 153E is illustrated in FIG. 48. Side walls 155 ofthe inductor core 154 can be vertically aligned with the side walls 28of the silicon buffer layer 26 by masking, patterning and etching steps.The photoresist 27 can be removed and the process continues with theformation of the conductive runners and vias, in accordance with theprocess steps illustrated in FIGS. 25 through 44, wherein the inductorcore 154 replaces the inductor core 40 of the previously describedembodiment.

In another embodiment, beginning with the structure of FIG. 49, anotherprocess for forming a ferromagnetic core is illustrated. With all theregions except the silicon buffer growth surface region 26 masked withphotoresist 27, a SiO2 layer 160 (about 100 mm thick) is deposited orgrown over the silicon buffer 26. Next a silicon layer 162 (e.g.,polysilicon or amorphous silicon) about 100 nm thick is formed over theSiO2 layer 160 to serve as a buried oxide layer. The thickness of thesilicon layer 162 is chosen to provide a sufficient barrier to blocksubsequently implanted metal ions from reaching the SiO2 layer 160.Hydrogen is implanted into the structure (as represented by arrowheads164) with sufficient energy and dose so that most of the hydrogen atomsare driven into the silicon buffer 26. Helium or any other materialcapable of forming nano-cavities as discussed below, can be used in lieuof hydrogen. After a local thermal anneal, such as a laser anneal (whichadvantageously avoids heating the entire structure to a temperature thatcan change the dopant profiles and impair the metalized interconnects,but permits the implanted hydrogen impurities to diffuse), a layercomprising nano-cavities 166 (with each cavity about 10 to 130 nm indiameter) is formed in an upper region of the silicon buffer 26. SeeFIG. 50.

As shown in FIG. 51, nickel, cobalt, iron, gadolinium or anotherferromagnetic metal is then implanted, as represented by arrowheads 170,with a sufficient dose level and implant energy to drive the ions intothe silicon layer 162 but not into the SiO2 layer 160. The ferromagneticmaterial is diffused downwardly through the silicon dioxide layer 160such that it precipitates into the nano-cavities 166 to create a band offerromagnetic domains 172, thereby forming an inductor core 180. SeeFIG. 52. During this process, the increased surface area and defects ofthe nano-cavities 166 within the silicon layer 26 cause thenano-cavities 166 to serve as sinks for silicon self-interstitials,which in turn lowers the nucleation barrier for the ferromagneticmaterial to precipitate into the nano-cavities. Additional successivelayers of silicon dioxide and silicon can be formed over the siliconlayer 162 to form additional layers of nano-cavities 172 in the siliconlayers. Ferromagnetic materials are implanted, as in FIG. 51, andprecipitate to the silicon layer forming additional layers ofnano-cavities 172 as in FIG. 52.

The silicon layer 162 and the SiO2 layer 160 can be removed by etchingif necessary. The structure can then be masked and etched to remove thephotoresist 27 and align side walls 182 of the silicon buffer 26 withthe edges 184 of the trench 42, as shown in FIG. 53. Formation of theremaining inductor structures continues with the process steps describedin conjunction with FIGS. 25 through 44, with the inductor core 180replacing the inductor core 40.

Advantageously, the multilayer inductor, including the various coreembodiments, formed according to the teachings of the present inventionis fabricated within the conventional metal layers of an integratedcircuit (with the inductor formed as a helical conductor structure). Thefabrication processes are compatible with conventional CMOS backend(i.e., interconnect) processing and the resulting structure offers ahigher Q and lower resistance in a relatively compact area than priorart inductors formed within an integrated circuit structure. When theconductive structures are formed of copper, the resulting conductor hasa lower resistance than those formed with aluminum, and thus theinductor exhibits a still higher Q. A larger inductor cross-sectionalarea results in those embodiments employing metal layers at spaced apartlevels of the substrate (for example, metal-1 to metal-3 or metal-3 tometal-5), which results in a higher inductance value. As illustrated bythe processing steps discussed above, the inductor is highlyintegratable either on-chip with other active elements or as part of amulti-module device constructed on a common substrate. The use of arelatively small volume of conductive material in the inductor conductorstructure lowers the eddy current losses when compared with prior artinductors. Also, the magnetic circuit lines are more concentrated due tothe compact inductor structure. Thus the inductance is increased and theeffect on proximate regions of the integrated circuit is reduced.

The present invention can also be applied to form a transformer,comprising two interacting windings where the magnetic field lines ofone winding (the primary winding) cut across the windings of the secondwinding and induce a voltage therein (the secondary winding).Incorporation of the aforedescribed ferromagnetic core material in thetransformer increases the winding inductance. Details of a transformerto which the teachings of the present invention can be applied can befound in commonly-assigned patent application entitled, A Thin FilmMultilayer High Q Transformer formed in a Semiconductor Substrate, filedon Oct. 5, 2001, and assigned application Ser. No. 09/972,481, which ishereby incorporated by reference.

An architecture and process have been described as useful for forming aferromagnetic core for a multilayer high Q inductor on a semiconductorsubstrate. While specific applications of the invention have beenillustrated, the principals disclosed herein provide a basis forpracticing the invention in a variety of ways and in a variety ofcircuit structures. Numerous variations are possible within the scope ofthe invention, including the use of any two metal layers to form theinductor conductors. The invention is limited only by the claims thatfollow.

1. A method for forming an integrated circuit structure comprising:providing a semiconductor substrate having an upper surface; forming afirst plurality of conductive lines in a first layer overlying the uppersurface; forming a second plurality of conductive lines in a secondlayer spaced apart from and overlying the first layer; interconnectingthe first and the second plurality of conductive lines to form a helicalconductor structure; and forming semiconductor material islandsexhibiting ferromagnetic properties between the first and the secondlayers wherein the step of forming semiconductor material islandsfurther comprises: (a) forming a silicon layer between the twointerconnected conductor layers, wherein the silicon layer has a topsurface; (b) forming a semiconductor material layer on the top surface;and (c) forming the semiconductor material islands from thesemiconductor material layer; and Wherein the step (c) further comprisesannealing the integrated circuit structure to form the semiconductormaterial islands, and wherein the duration and temperaturecharacteristics of the annealing step affect the density and spacing ofthe semiconductor material islands.
 2. The method of claim 1 furthercomprising forming a plurality of conductive vias connecting terminalends of each one of the second plurality of conductive lines to terminalends of two successive conductive lines of the first plurality ofconductive lines, such that one of the second plurality of conductivelines conductively spans two successive conductive lines of the firstplurality of conductive lines to form the helical conductor structure.3. The method of claim I wherein the step of forming the material layercomprises forming a crystalline material layer with spaced apartferromagnetic elements incorporated therein.
 4. The method of claim 1wherein the step (b) further comprises forming a germanium layer havinga thickness of about five to thirty angstroms.
 5. The method of claim 1wherein the steps (a) through (c) are repeated to form a plurality oflayers each comprising semiconductor material islands.
 6. A method forforming an integrated circuit structure comprising: (a) providing asemiconductor substrate having an upper surface; (b) forming a firstplurality of substantially parallel conductive strips in a first planesubstantially parallel to the upper surface; (c) forming a secondplurality of conductive strips in a second plane substantially parallelto the first plane; (d) interconnecting terminal ends of each one of thesecond plurality of conductive strips to terminal ends of two successiveconductive strips of the first plurality of conductive strips, such thatone of the second plurality of conductive strips conductively spans twosuccessive conductive strips of the first plurality of conductivestrips; and (e) forming a layer of laterally spaced-apart and discretesemiconductor material regions between the first and the second planes,the material regions exhibiting ferromagnetic properties.
 7. The methodof claim 6 wherein the step of forming the semiconductor materialregions further comprises forming a semiconductor layer, forming quantumdots within the semiconductor layer, forming a layer of ferromagneticmaterial over the quantum dots, wherein the ferromagnetic material isselected from among cobalt, iron, nickel and gadolinium and annealingthe integrated circuit structure to form ferromagnetic material from theferromagnetic layer in the quantum dots.
 8. The method of claim 6wherein the steps (e) through (e) are repeated to form a plurality ofmaterial region layers.
 9. A method for forming an integrated circuitstructure comprising: (a) providing a semiconductor substrate having anupper surface; (b) forming a first plurality of substantially parallelconductive strips in a first plane substantially parallel to the uppersurface; (c) forming a second plurality of conductive strips in a secondplane substantially parallel to the first plane; (d) interconnectingterminal ends of each one of the second plurality of conductive stripsto terminal ends of two successive conductive strips of the firstplurality of conductive strips, such that one of the second plurality ofconductive strips conductively spans two successive conductive strips ofthe first plurality of conductive strips; (e) forming a first siliconlayer between the first and the second planes; (f) forming a pluralityof nano-cavities in the first silicon layer; and forming ferromagneticmaterial in the plurality of nano-cavitles.
 10. The method of claim 9wherein the step (f) further comprises: (f1) forming a silicon dioxidelayer overlying the first silicon layer; (f2) forming a second siliconlayer overlying the silicon dioxide layer; (f3) implanting nano-cavityforming ions wherein the implant energy is selected to drivesubstantially all of the ions into the first silicon layer; (f4)annealing the integrated circuit structure causing the formation of aplurality of nano-cavities in the first silicon layer.
 11. The method ofclaim 10 wherein the step (g) further comprises implanting aferromagnetic material having an implant energy selected to drive theferromagnetic material into the second silicon layer and annealing theintegrated circuit structure to precipitate the ferromagnetic materialinto the plurality of nano-cavities.
 12. The method of claim 10 whereinthe step (f1) comprises forming a silicon dioxide layer having athickness of about 100 nanometers.
 13. The method of claim 10 whereinthe step (f2) comprises forming a second silicon layer having athickness of about 100 nanometers.
 14. The method of claim 9 wherein theferromagnetic material is selected from among nickel, iron, cobalt andgadolinium.
 15. The method of claim 9 wherein the steps (e) and (g) arerepeated to form a plurality of ferromagnetic material layers.
 16. Amethod for forming an integrated circuit structure comprising: providinga semiconductor substrate having an upper surface; forming a firstplurality of substantially parallel conductive strips in a first planesubstantially parallel to the upper surface; forming a second pluralityof conductive strips in a second plane substantially parallel to thefirst plane; interconnecting terminal ends of each one of the secondplurality of conductive strips to terminal ends of two successiveconductive strips of the first plurality of conductive strips, such thatone of the second plurality of conductive strips conductively spans twosuccessive conductive strips of the first plurality of conductivestrips; forming a silicon layer between the first and the second planes,wherein the silicon layer has a top surface; forming a semiconductormaterial layer on the top surface; and forming a plurality ofsemiconductor quantum dots from the semiconductor material layer; andforming ferromagnetic material in the quantum dots.
 17. The method ofclaim 16 wherein the step of forming the plurality of semiconductorquantum dots further comprises annealing the structure.
 18. A method forforming, within a semiconductor substrate, an inductor having a coreexhibiting ferromagnetic properties, comprising: providing asemiconductor substrate; forming a first stack of insulating layers overthe semiconductor substrate; forming a plurality of substantiallyparallel first trenches within one or more layers of the first stack ofinsulating layers; forming conductive material within each one of theplurality of first trenches to form a plurality of substantiallyparallel first level metal runners; forming laterally spaced-apart anddiscrete semiconductor material regions exhibiting ferromagneticproperties within or overlying the plane of the plurality of first levelmetal runners; forming a second stack of insulating layers overlying thefirst stack of insulating layers; forming a plurality of first andsecond conductive vias within the second stack of insulating layers,wherein a bottom surface of each one of the plurality of first andsecond conductive vias is in electrical contact with a first end and asecond end, respectively, of each one of the plurality of first levelmetal runners; forming a third stack of insulating layers overlying thesecond stack of insulating layers; forming a plurality of third andfourth via openings within the third stack of insulating layers, whereineach one of the plurality of third and fourth via openings is verticallyaligned with one of the plurality of first and second conductive vias,respectively; forming a plurality of substantially parallel secondtrenches within one or more layers of the third stack of insulatinglayers, wherein a first end and a second end of each one of theplurality of second trenches is aligned with one of the plurality ofthird via openings and fourth via openings, respectively, and whereineach one of the plurality of second trenches is disposed between twosuccessive first metal level runners; forming conductive material withinthe plurality of third and fourth via openings and the plurality ofsecond trenches to form a plurality of third and fourth conductive viasand a plurality of second level metal runners in electrical contacttherewith, wherein each one of the plurality of third and the fourthconductive vias is in electrical contact with one of the first and thesecond plurality of conductive vias, respectively, and wherein one ofthe plurality of second level metal runners conductively spans twosuccessive first level metal runners.
 19. The method of claim 18 whereinthe step of forming the material regions exhibiting ferromagneticproperties further comprises: forming a silicon layer within oroverlying the plane of the plurality of first level metal runners,wherein the silicon layer has a top surface; forming a silicon dioxidelayer on the top surface; forming a semiconductor material layeroverlying the silicon dioxide layer: forming quantum dots from thesemiconductor material layer: forming a layer of ferromagnetic materialover the quantum dots; and annealing the integrated circuit structure toform the ferromagnetic material in the quantum dots.
 20. The method ofclaim 18 wherein the step of forming the material regions exhibitingferromagnetic properties further comprises: forming a first siliconlayer within or overlying the plane of the plurality of first levelmetal runners; forming a plurality of nano-cavities in the first siliconlayer; and forming ferromagnetic material in the plurality ofnano-cavities.
 21. The method of claim 18 wherein the step of formingthe material regions exhibiting ferromagnetic properties furthercomprises: forming a silicon layer within or overlying the plane of theplurality of first level metal runners, wherein the silicon layer has atop surface; forming a semiconductor material layer on the top surface;and forming a plurality of semiconductor islands on the top surface,wherein the plurality of semiconductor islands exhibit ferromagneticproperties.
 22. A method for forming an integrated circuit structurecomprising an inner winding, a core, and an outer winding, wherein themethod comprises: forming a semiconductor substrate having an uppersurface therein; forming an outer winding comprising: forming spacedapart first upper and first lower conductor lines over the uppersurface; interconnecting the first upper and the first lower conductorlines to form a first helical conductor structure; forming an innerwinding comprising: forming a second upper and a second lower conductorlines between the first upper and the first lower conductor lines;interconnecting the second upper and the second lower conductor lines toform a second helical conductor structure about and approximatelyconcentric with the first helical conductor structure; and forminglaterally spaced-apart semiconductor material regions exhibitingferromagnetic properties within the second helical conductor structure.23. The method of claim 22 wherein the step of forming the semiconductormaterial regions exhibiting ferromagnetic properties further comprises:forming a silicon layer within the second helical structure; forming asilicon dioxide layer over the silicon layer; forming a semiconductormaterial layer overlying the silicon dioxide layer: forming quantum dotsfrom the semiconductor material layer: forming a ferromagnetic materiallayer over the quantum dots: and annealing the integrated circuitstructure to form the ferromagnetic material in the quantum dots. 24.The method of claim 22 wherein the step of forming the semiconductormaterial regions exhibiting ferromagnetic properties further comprises:forming a first silicon layer within the second helical structure;forming a plurality of nano-cavities in the first silicon layer; andforming ferromagnetic material in the plurality of nano-cavities. 25.The method of claim 22 wherein the step of forming the semiconductormaterial regions exhibiting ferromagnetic properties further comprises:forming a silicon layer having a top surface within the second helicalstructure; forming a semiconductor material layer on the top surface;and forming a plurality of semiconductor islands on the top surface,wherein the plurality of semiconductor islands exhibit ferromagneticproperties.
 26. An integrated circuit structure, comprising: asemiconductor substrate; a helical conductor formed over the substrate;and a core comprising laterally spaced-apart discrete semiconductormaterial regions exhibiting ferromagnetic effects formed in a regionbounded by the helical conductor.
 27. The integrated circuit structureof claim 26 wherein an axis of the helical structure is substantiallyparallel to an upper surface of the semiconductor substrate.
 28. Theintegrated circuit structure of claim 26 wherein the core comprises aplurality of substantially parallel material layers each layercomprising the laterally spaced-apart discrete material regionsexhibiting ferromagnetic effects.
 29. The integrated circuit structureof claim 26 wherein the discrete material regions comprises quantum dotsformed in one or more semiconductor land ferromagnetic materialencapsulated within the quantum dots.
 30. The integrated circuitstructure of claim 29 wherein the ferromagnetic material is selectedfrom among cobalt, iron, nickel and gadolinium.
 31. The integratedcircuit structure of claim 26 wherein the discrete material regionscomprise semiconductor material islands.
 32. The integrated circuitstructure of claim 26 wherein the discrete material regions comprisesnanocavities formed in a silicon layer and ferromagnetic material formedwithin the nanocavities.
 33. The integrated circuit structure of claim32 wherein the ferromagnetic material is selected from among cobalt,iron, nickel and gadolinium.
 34. The integrated circuit structure ofclaim 26 wherein the helical conductor comprises a plurality ofconcentric connected windings, and wherein each winding is in the shapeof a rectangle.
 35. The integrated circuit structure of claim 34 whereineach one of the plurality of windings comprises: a first lowerconductive strip overlying the semiconductor substrate; a firstconductive via having a lower surface connected to a first terminal endof the lower conductive strip; a upper conductive strip spaced apartfrom the lower conductive strip and having a first terminal endconnected to an upper surface of the first conductive via; a secondconductive via having an upper surface connected to a second terminalend of the second conductive strip, wherein a lower surface of thesecond conductive via is connected to a first terminal end of a secondlower conductive strip forming a portion of the next winding of thehelical conductor.
 36. The integrated circuit structure of claim 35,wherein the core comprises a plurality of core segments, and wherein oneof the plurality of core segments is positioned between the first andthe second lower conductive strips.
 37. The integrated circuit structureof claim 35, wherein the core comprises a plurality of core segments,and wherein a lower conductive strip substantially surrounds a coresegment.
 38. An integrated circuit structure comprising: a semiconductorsubstrate; a plurality of substantially parallel first conductive stripsoverlying the semiconductor substrate; a first stack of conductive viasin electrical connection with a first end of each one of the pluralityof first conductive strips; a second stack of conductive vias inelectrical connection with a second end of each one of the plurality offirst conductive strips; a plurality of second conductive strips havinga first end in electrical connection with the uppermost via of the firststack of conductive vias and a second end in electrical connection withthe uppermost via of the second stack of conductive vias, wherein one ofthe plurality of second conductive strips conductive spans twosuccessive first conductive strips; and a core comprising laterallyspaced-apart discrete semiconductor material regions exhibitingferromagnetic properties disposed between the first and the secondconductive strips for increasing the inductance of the integratedcircuit structure.
 39. The integrated circuit structure of claim 38wherein the discrete material regions comprises having a plurality ofquantum dots, and wherein ferromagnetic material is encapsulated withinthe quantum dots.
 40. The integrated circuit structure of claim 39wherein the ferromagnetic material is selected from among cobalt, iron,nickel and gadolinium.
 41. The integrated circuit structure of claim 38wherein the discrete material regions comprises a silicon layer having aplurality of nanocavities therein, and wherein ferromagnetic material isdisposed within the nanocavitles.
 42. The integrated circuit structureof claim 41 wherein the ferromagnetic material is selected from amongcobalt, iron, nickel and gadolinium.
 43. The integrated circuitstructure of claim 38 wherein the discrete material regions comprisesemiconductor material islands.
 44. The integrated circuit structure ofclaim 43 wherein the ferromagnetic material is selected from amongcobalt, iron, nickel and gadolinium.
 45. The integrated circuitstructure of claim 38 wherein the core material comprises a plurality ofstacked material layers each layer comprising the discrete materialregions exhibiting ferromagnetic properties.
 46. A multi-levelintegrated circuit structure, comprising: a semiconductor substratehaving a plurality of insulating layers and a plurality of conductivelayers therebetween; runner conductive portions; vertical conductiveportions; wherein lower runner portions are formed in a lower conductivelayer of the semiconductor substrate; wherein upper runner portions areformed in an upper conductive layer above the lower runner portions;wherein two or more vertically aligned first via portions effectelectrical connection between a first end of a first lower runnerportion and an overlying first end of a first upper runner portion;wherein two or more vertically aligned second via portions effectelectrical connection between a first end of a second lower runnerportion and an overlying second end of the first upper runner portion;and a material layer comprising laterally spaced-apart discretesemiconductor material regions exhibiting ferromagnetic propertiesdisposed between the lower runner portions and the upper runnerportions.
 47. The multi-level integrated circuit structure of claim 46wherein the runner conductive portions and the vertical conductiveportions form a helical inductor, and wherein the material layerexhibiting ferromagnetic properties comprises an inductor core.
 48. Anintegrated circuit structure comprising: a semiconductor substratehaving an upper surface therein; an outer winding comprising first upperand first lower conductor layers over the upper surface; conductive viasinterconnecting the first upper and the first lower conductor layers toform a first helical structure; an inner winding comprising a secondupper and a second lower conductor layer between the first upper and thefirst lower conductor layers; conductive vias interconnecting the secondupper and the second lower conductor layers to form a second helicalstructure within the first helical structure; and a core comprisinglaterally spaced-apart discrete semiconductor material regionsexhibiting ferromagnetic properties, the core within a region bounded bythe second upper and the second lower runners.